When debugging, the user canbe sure that he is not accidentally impacting the power profile of the system. Thisdebugging mode is also referred to as stop mode debugging. Of course VPs also ...

Debugging a large system with many power rails can be challenging. However, don’t panic, a PMBus design combined with good software tools can make the job much easier. In this post we will look at a ...

Simulation-based debug challenges arise when verifying the behavior of a power-managed SoC from the front-end design phase through the back-end implementation phase. We'd also like to recognize the ...

In previous blogs, we’ve talked about UPF and the successive refinement low power flow developed by ARM and Mentor Graphics (you can find these here.) In this blog we’d like to walk through some ...

Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and ...

PowerTheater-Explorer, an option to Sequence Design’s PowerTheater RTL power-analysis engine, adds power-visualization and debug capabilities for fast, interactive power reduction. By adding ...